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Rambus

The newly established Interconnect Business Unit is hiring a PE Principal DFT lead to architect, design, implement, verify, test and support all aspects of DFT on complex SoCs at advanced process technology nodes (14nm/10nm/7nm) using advanced DFT methodologies.

Position can be located in – San Jose, California; Raleigh, North Carolina, Vancouver, Canada, or other US / Canada or Banglore, India locations.

Responsibilities

Proven expertise in Test architecture definition for complex multi-million gate SoCs
Strong understanding of DFT concepts and advanced methodologies
Proven hands-on SoC experience in:
Scan and ATPG for different fault models
MBIST insertion, implementation, and verification
Boundary scan, ACJTAG, IEEE 1500 implementation and verification
IEEE1687 (iJTAG) and fault grading for functional manufacturing tests
Logic BIST understanding and expertise
Exposure and understanding Loopback testing is a bonus
and more…

For additional details and most recent updates, hit “Apply for job”