Have full ownership of Analog IP, its major blocks or sub blocks
Define the architecture and uArchitecture of the IP’s and its sub functions
Understand and disseminate applicable standards and its relevance in a given project to the team
Responsible to develop and design the high speed circuit blocks used in Rambus
Design, simulate and characterize high performance CMOS data communication circuits (drivers, receive equalizers, PLLs, high speed samplers, clock recovery circuits).
Responsible for Receiver, transmitter or PLL level designs and top level ownership.
The designer will be responsible for all aspects of designs such as schematic capture, layout review, simulation & analysis of critical electrical and timing parameters, documentation and silicon bring-up.
Will be responsible to work with the system engineering team for Silicon bring up and Characterization.
Mentoring of junior designers where applicable.

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