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Rambus

Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our architecture licenses, IP cores, chips, software, and services span memory and interfaces, security and emerging technologies to positively impact the modern world.

 

Our customers are leading chip and system design firms, foundries, and service providers. Our products are integrated into tens of billions of devices and systems. They power and secure diverse applications in a growing number of target segments including data center, networking, AI, automotive and IOT.

 

Rambus is seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to develop products that have real life impact.

 

This is a highly impactful position for the System Solutions Engineering team of the Rambus IP Cores division.  We are looking for a highly-experienced leader to build, lead and drive direction in signal and power integrity in advanced SerDes PHY development.  You will participate in IP generation and technology evangelization and contribute towards new product initiatives leveraging this critical IP. You are a team player with excellent written and verbal communication skills, and you are self-motivated and detail-oriented with the ability to work with peers across groups and projects.

Responsibilities
Leadership role in building a strong global organization driving robust SI/PI hardened advanced interface memory and SerDes IP products
Define advanced architectures and specifications for robust multi-protocol SerDes IP solutions together with the architecture and design teams
Develop Signal and Power Integrity methodologies for the analysis, modeling and simulation of link channels and global power distribution
Build voltage, timing and power supply budgets across channel components including noise effects (reflections, simultaneous switching noise and crosstalk)
Design, analyze and document guidelines for full link interconnect
Perform channel margin analysis to provide design tradeoffs between package, board, connector and cables
Develop IBIS AMI IO and package/system channel simulation models
Correlate Tx and Rx SerDes simulation models with measurements
Perform system level timing analysis to implement SI guidelines and checklists
Best in class team validated though customer interactions, patent development, conference and journal publications

For more details, hit “Apply for job”