Why you want this job:

Rambus is engaged in the design of high end IP cores such as 112G SERDES, GDDR6 Memory PHYs and Buffer Chip product ICs, and provides a rare opportunity to work on these cutting-edge designs.
Project ownership, chance to drive the projects, and share ideas across highly technical functional groups.
Package design projects are impactful with real performance feedback coming from both in-house test chips, products, and from customer ASICs build with your design inputs.
Rambus is looking for an experienced IC signal integrity/power integrity/package design engineer for the Systems Engineering team in the IP Business Unit. The suitable candidate will be involved in the design and development phase of both high-speed complex IP PHY development, as well as semiconductor product chips targeting leading edge high speed SerDes and Memory PHYs.


You will be responsible for completing SI/PI modelling and analysis of the memory/SerDes system channel comprising of die, package, and PCB. You will be responsible for SI Channel simulations, PDN Noise analysis, and ensuring that all the channel components meet the electrical signal integrity and power integrity requirements of the product. You will make recommendations on package and PCB routing, bump-layout on the die, and BGA pin arrangement on the PCB.


Recommend package layer stack-up, material, impedance targets and net assignments for signals
Complete package designs and parasitic extractions for Rambus products and IP Phys
Optimize single-ended/differential insertion loss, return loss, cross-talk for signals and high speed buses
IR Drop and PDN optimization in packages/interposers. Recommend caps on packages
Complete system level PDN analysis and recommend decoupling strategies
Optimize and implement routing for high-speed signals and power planes
Document design guidelines for package designs
Proactively work on documentation in the form of user guide and integration guide to address customer integration questions.
Design BGA packages for high frequency integrated circuits using Allegro Package Designer using SIP Layout
Develop package designs for signals exceeding 100Ghz GHz using RF transmission lines
Complete package extractions (signal and power) using Cadence tools (PowerSI) and Ansys tools (Electronics Desktop, HFSS, SiWave)
Complete system level PDN analysis using Keysight ADS, HSPICE
Complete transient channel simulation using Keysight ADS, HSPICE

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