Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our architecture licenses, IP cores, chips, software, and services span memory and interfaces, security and emerging technologies to positively impact the modern world.


Our customers are leading chip and system design firms, foundries, and service providers. Our products are integrated into tens of billions of devices and systems. They power and secure diverse applications in a growing number of target segments including data center, networking, AI, automotive and IOT.


Rambus is seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to develop products that have real life impact.


Why you want this job:

Rambus is engaged in the design of high end IP cores such as 112G SERDES, GDDR6 Memory PHYs and Buffer Chip product ICs, and provides a rare opportunity to work on these cutting-edge designs.
Project ownership, chance to drive the projects, and share ideas across highly technical functional groups.
Package design projects are impactful with real performance feedback coming from both in-house test chips, products, and from customer ASICs build with your design inputs.
Rambus is looking for an experienced IC signal integrity/power integrity/package design engineer for the Systems Engineering team in the IP Business Unit. The suitable candidate will be involved in the design and development phase of both high-speed complex IP PHY development, as well as semiconductor product chips targeting leading edge high speed SerDes and Memory PHYs.


You will be responsible for completing SI/PI modelling and analysis of the memory/SerDes system channel comprising of die, package, and PCB. You will be responsible for SI Channel simulations, PDN Noise analysis, and ensuring that all the channel components meet the electrical signal integrity and power integrity requirements of the product. You will make recommendations on package and PCB routing, bump-layout on the die, and BGA pin arrangement on the PCB.

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