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Rambus

As a design verification engineer, the candidate will be reporting to digital engineering director and is a Full-Time position. The team is working on the next generation multi-protocol SERDES Phy IP. The design verification engineer will have full ownership over the IP verification planning and execution and will be expected to interact extensively with digital, analog and system engineers in the team.

Responsibilities:

Composing detailed verification plans while working closely with the digital design and system teams
Developing randomly constrained and automated UVM or similar test environments for RTL and GL DUTs with multi voltage and clock domains and incorporating analog and mixed signal behavioral models and 3rd party IPs
Developing test cases to match algorithm model and/or mixed signal model for the SERDES IP
Running coverage regressions to meet the defined coverage goals
Tracking and communicating verification status, issues, and concerns
Interact with application team and customers on bring-up issues, firmware development and design integration.

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