Memory and interfaces are in our DNA. Leveraging over two decades of high-speed circuit design leadership, we make high-performance, low-power memory and serial link interface chips and IP cores to meet the needs of increasingly diverse enterprise and mobile applications. Featuring proven IP and advanced technology, our product families include server DIMM chipsets, R+ DDRn PHYs and R+ Serial Link PHYs.

The Physical Design Engineer (all levels) will assume an implementation & design role at Rambus. The primary activity will be to develop multidimensional designs involving the layout of complex integrated circuits, from Schematic to GDSII implementation and from Floor planning to Post-Layout verifications. The successful candidate will also support executing, deploying, and supporting analog and physical design, methodologies, and flows associated with the design of high speed mixed-signal ICs.  Prepares and presents reports outlining the status and come up with actions necessary to achieve optimal layout design.

Responsible for physical layout implementation of analog and digital blocks for mixed signal integrated circuits
Ownership of floor planning, abstract creation, new layout, porting and other modifications to existing layout, routing, and place & route merges, signal integrity analysis, extraction, EM/IR fixes & physical verification
Develop and support nanotechnology CMOS physical design flow
Develop and maintain Mixed Signal physical design methodology
Evolve and Support the Schematic/RTL 2 GDSII flow
Maintain Technology environment, custom digital cells and custom analog IP libraries
Support physical verification environment
Mentor junior engineers by providing technical direction in physical layout design

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