We’re seeking a highly motivated and innovative Senior Digital Design Engineer with knowledge of ASIC development flow. You would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation NRZ and PAM-based SerDes products. Sound theoretical and practical background in high-speed serializer and data recovery circuits is a plus. The position offers an excellent opportunity to work with an experienced team of digital and mixed-signal engineers accountable for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.


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