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SeviTech Systems Pvt Ltd

One of the Best VLSI Services Company

STA Engineers (Static Timing Analysis Expert)

Location: Bangalore

Experience: 2 – 10 Years

Desired Skills:

B. Tech. / M. Tech. with 2 -8 years of experience in Synthesis, STA
Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains
Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff
Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Displayetc…)
Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm
Good knowledge of EDA tools from RC, DC, PT, PTSIExperience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
Good knowledge of VLSI process and device characteristics
Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting

Share your CV to priyanka.s@sevitechsystems.com if it matches to your profile.

Else you can share some references if someone is in need of the job , thanks in advance .