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Siemens EDA

We are looking for a highly capable and a dedicated Senior Verification Engineer to join our growing team in Cambridge. Successful applicants will have the opportunity to enjoy shaping the development of ground-breaking silicon IP, which is already changing the way systems and software created around complex SoC devices with multiple heterogeneous processors are optimized and debugged.

What do you need?

Demonstrable experience of creating and developing testbenches and checking the functionality of IP blocks
Experience of formulating and writing System Verilog coverage statements
Strong competence with System Verilog and Verilog
An active exposure to UVM or OVM environments
Ability and willingness to get to the root of a test failure
The ability to work as part of a team and under pressure in a fast paced environment
Being a self-starter with a desire to solve problems is key

For more & updated details, hit “Apply for job”