As a creative verification engineer with a knowledge of subsystems and SoCs you will be part of a team tasked with verifying functional correctness of compute subsystems. You will work with the project team to understand and review the subsystem architecture and design specifications, and to build a functional verification strategy.


Your key responsibilities will include crafting test plans, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. You will also contribute to developing and improving the verification methodologies used by the team. In addition, you’ll work closely with other teams on the design microarchitecture, verification methodologies, system performance, etc.



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