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Siemens

The candidate will be responsible for designing, developing, troubleshooting, and debugging software programs in the RTL logic synthesis Tool with a focus on logic optimization techniques, timing-driven netlist optimizations, interfacing with synthesis, and incremental timing engines to achieve competitive PPA on advanced node technologies for RTL-2-GDSII flow. The candidate will work in close coordination with the cross-geographical team to deliver innovative solutions and enhance/maintain RTL logic synthesis tool features.

 

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