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Arm

Architect, implement and validate innovative DFT techniques on test chips and hard macros. Insert DFT logic into SoC style designs at the RTL level and the Synthesis gate level, validate all features and generate ATE-targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on DFT gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.

 

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