Provides pre-sales, post-sales technical expertise for the VIP and transactor engagements. May be involved in understanding of customer’s design verification requirements in details along with architecting and developing customer’s SV/UVM testbench by integrating Synopsys Verification IPs. Also, get involved in creating testbench components like scoreboard, coverage model tests etc. along with debugging the testbench issues.

Key QualificationsCandidate should have good understanding of ASIC verification flow – RTL verification VLSI, and/or CAD engineering.
Strong communication skills are required.
Candidate should have worked extensively using verification methodologies like UVM/OVM & VMM.
Is proficient with UNIX/PERL, HDL (Verilog/VHDL).
Knowledge of any of AMBA, USB, PCIE, Ethernet, DDR Protocols is must along with the development or usage of Verification IP.
Possesses a solid understanding of specialization area plus working knowledge of one other related area.
Resolves issues in creative ways.
Exercises independent judgment in selecting methods and techniques to obtain solutions.
Executes projects from start to completion.
Contributes to moderately complex aspects of a project.
Determines and develops recommendations to solutions.
Works on team-driven or task-oriented projects.
May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.

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