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Synopsys

The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. He/ She will work closely with RTL designers and be part of a global team of expert Verification Engineers.
Will be working on the next generation Ethernet protocols for commercial, Enterprise and Automotive applications
Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and analysis and meeting quality metric goals and regression management.

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