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Synopsys

Seeking a highly motivated and innovative mixed signal co-simulation verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation 50G/100G SERDES products.

The position offers an excellent opportunity to work with an expert team of digital, analog and mixed signal engineers responsible for delivering high-end mixed-signal designs.  Responsibilities include:modifying/using the existing UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs;
analyzing/verifying the functionalities of SERDES;
Defining and tracking verification testplans;
Debugging simulation failures in both analog and digital domains;
Creating top level analog testbenches for SERDES;
Performing physic layout reliability analysis for SERDES;
Candidates should have experience writing scripts in languages such as Perl, Python  and Unix shell.  The ideal candidate would be familiar with Verilog and SystemVerilog.

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