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Synopsys

In this role, you will contribute to the design of and verification of advanced high speed NRZ and PAM-4 SERDES IP in the latest FinFET technology nodes. Besides taking responsibility for the architecture, design and implementation of full-custom blocks (e.g. serializer, de-serializer, clock path), you will enforce a rigorous verification methodology of various full custom blocks. You will generate digital models of analog blocks, representing functionality, timing and impairments. With many analog blocks requiring digital correction to operate within specification, the co-verification of full custom logic and RTL will be essential.

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