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Synopsys

SerDes System Architecture, Senior Designer

You will be part of an R&D team developing 32Gbps NRZ and 112Gbps PAM4 serial-link transceivers. You will work with a cross functional design team of analog and digital designers, and hardware engineers.

You will be involved in all stages of development including:

Architecture: definition of architecture and specifications for the transmitter and receiver
Modelling:   design and maintenance of the system level model
Sign-off: system level simulation of the design performance across multiple protocols and channels
Silicon: qualification and correlation of performance and algorithms in silicon
Customers:  assisting customers on system level performance and algorithmic issues

For additional details and most recent updates, hit “Apply for job”