Signal and Power Integrity R&D Engineer, Sr I

Responsible for system interface interconnect review, modeling, simulating, analyzing both signal and power integrity (SIPI) effects, troubleshooting and debugging. This encompasses all aspects of physical interconnect in a system context, including both RX/TX die/silicon, package, pcb, connectors and components on multi-signal transmission line interfaces such as DDR/SERDES. Performs, verifies and documents interface SIPI analysis outcome as part of customer services. Carry out experiments to validate modeling and methodologies. Develop and document SIPI requirements, flows and methodologies for internal/external customer use.

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