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Synopsys

Job Description

The candidate will be part of the DesignWare IP DDR Controller R&D team at Synopsys in Dublin, Ireland.  The successful candidate will perform a key role in linking the front-end RTL design with the back-end physical design.
The successful candidate will drive alignment between the RTL design team and physical design team. They will provide technical leadership to the physical design team on the physical implementation of the controller and technical leadership to the RTL design team on the creation of designs to meet every more demanding timing-closure challenges.
They will be strong in RTL synthesis, constraint generation/validation and timing analysis. They will be capable of generating sub-systems consisting of controller, PHY and SRAM. They will be capable of defining floorplans and pushing the design through front-end placement flows. The successful candidate will be very familiar with physical design.
The successful candidate will be responsible for the handoff from RTL design to physical design and will be responsible for writing customer implementation guides.

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