You will be a member of a high-performing R&D team developing the market-leading interconnect parasitic extraction tool StarRC. StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. Research, design, and development of innovative solutions to complex problems leading to highly differentiated and high-quality production software. Designing very efficient data structure and algorithms. Modeling interconnect capacitance and inductance for advanced process technologies using pattern-matching and field solver based methods. Developing, debugging and maintaining complex software written in C/C++, taking ownership of specific customer and tool integration issues, communicating status within R&D and to management, working independently or in a team.

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