中文 English

Synopsys

Responsible for designing, developing, troubleshooting, and/or debugging start-of-the-art clock tree synthesis, optimization and concurrent clock and data optimization within our rtl to gds implementation solution. Drive innovation in design, development, troubleshooting and debugging of the software. Results driven and customer driven.

The candidate should have strong C++ programming and UNIX skills along with excellent problem solving and algorithm development skills. The candidate must be familiar with software development process, debugging tools, and configuration management concepts. Prior experience and education in timing analysis, placement, routing, clock tree synthesis, and/or gate level optimization algorithms is desired.

For more & updated details, hit “Apply for job”