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Synopsys

The engineer will join the SEV group and will be part of the FPGA prototyping software R&D team based at the R&D site at Wissous, Paris Region. In this role you will contribute to the development of FPGA prototyping/emulation software, including the support and modeling of the FPGA board, automatic partitioning, placement and routing on the board, timing analysis and timing optimisation, netlist optimisation and database generation for FPGA place and route. You will be involved in the complete chain of the software development process, starting from specification, code development, validation through customer designs, performance estimation and improvement.

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