Job Purpose and Mandate:
This position of “Mixed-Signal Verification Engineer” is a R&D Engineer whose mandate is to participate in the verification of mixed-signal logic blocks in compliance with the project’s specifications and Synopsys’ design methodologies.
The successful candidate will work on products that are part of the Synopsys IP portfolio, it presents the opportunity for the successful candidate to have their work used in many of the leading products that are developed by Synopsys customers.

Main duties:
• Participate in complex block and/or chip mixed-signal verification architecture studies
• Participate in the behavioral modeling activities using Verilog/SystemVerilog language
• Participate in the implementation of mixed-signal verification environments and testcase creation
• May participate in the development of verification environments using top of the edge methodologies: System Verilog and UVM
• Work toward improving efficiency in design procedures and methodologies
• Documentation of verification environments/plans and overall procedures
• Other related duties as assigned by the upper manager

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