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Synopsys

Designs & develops RTL for Highspeed circuits for 56Gbps serdes operation. Knowledge of tools  spyglass, DC, Formality, DFT is preferred.
Prior knowledge of serdes design is preferred. Scripting experience of tcl/perl is preferred.
Defines, develops semiconductor integrated circuit digital and mixed signal circuits. Generates design and verification specifications. Determines architecture design, logic design, test bench design, and test cases. Defines module interfaces and formats. Evaluates and exercises various aspects of the development flow which may include such items as RTL development, functional simulation, constraint development, design for test logic, synthesis, timing analysis, power analysis, behavioral modeling, and verification coverage metrics. Generates documentation for circuit development, test plans, verification environments, and usage. May participate in evaluation and troubleshooting of digital and mixed signal circuits. Defines, develops, and verifies semiconductor integrated circuit digital and mixed signal circuits. Generates design and verification specifications. Determines architecture design, logic design, test bench design, and test cases. Defines module interfaces and formats. Evaluates and exercises various aspects of the development flow which may include such items as RTL development, functional simulation, constraint development, design for test logic, synthesis, timing analysis, power analysis, behavioral modeling, and verification coverage metrics. Generates documentation for circuit development, test plans, verification environments, and usage. May participate in evaluation and troubleshooting of digital and mixed signal circuits.

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