Website
Synopsys

The position requires candidate having excellent exposure to ASIC Digital design expertise. The candidate should have: 1> Excellent understanding in RTL developing, verifying using Verilog and/or system Verilog simulator. 2> Have understanding on behavioral model development on analog circuits like PLL etc 3> Should have exposure generating the tester based vectors. 4> Has good debug capability (evaluating and troubleshooting digital circuits) 5> A strong desire to learn, explore & implement at new technologies. Demonstrates good analysis & problem-solving skills. Resolves issues in creative ways. 6> Has basic knowledge of timing concepts The position requires 6+ years of experience in Front End design cycle. Preference will be given to candidates possessing hands-on working knowledge in 16nm or below. This position requires BSEE with MSEE preferred

For more details, hit “Apply for job”