Synopsys IC Validator (ICV) is a comprehensive signoff DRC / LVS tool architected and proven for In-Design physical verification at leading-edge process nodes. It delivers excellent scalability, superior ease-of-use for the physical designer, and high programmability for easier runset development. The successful candidate would be working on development, qualification and optimization of advanced technology runsets.

With the advent of technology, the PV requirements have become very complex. As a result, the number of checks in runsets have increased multi-fold and warrant fairly challenging coding to meet the foundry requirements. The job requires engineer to develop high quality, high performance runsets, which enable Synopsys customers to validate their advanced technology chips for their manufacturability. Development of a runset involves visualization of hierarchical geometries and coming up with creative solutions to meet the design manual expectations. The quality of the runset is ensured by validating it against a specially designed regression suite whose qualification is a pre-requisite before the runset can be released for production use. The engineer is also expected to understand any new technology requirements which are currently not supported by the tool and work with R&D and CAE teams to define clear requirements for them. The job also involves handling customer issues which may require debugging runset issues on full chip designs.

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