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Synopsys

 

Responsibilities

– To define verification strategy and verification plans based on high level specification

–  Develop Testbenches using System Verilog and industry methodologies (Eg: OVM, UVM)

–  Good debugging skills to clean up the design issues.

–  Able to Write testcases in Assembly, System Verilog, UVM

– A minimum of  5+ years of experience in ASIC verification

– Deep knowledge and experience in RISC microprocessor architecture

– Hands-on experience in multi-core, cache coherency is a big plus

– Excellent grasp of Verification methodologies  (System Verilog, OVM, UVM)

 

– Familiar with EDA tools such as, VCS, VERDI, SPYGLASS, etc.

– Good knowledge of programming at assembly and C/C++ level

– Excellent communications skills in English

– Good demonstration of enthusiasm, drive and diligence

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