中文 English

Synopsys

Job Description and Requirements

Solid understanding in device physics in deep submicron CMOS technologies such as 7nm/5nm FinFET
Should have very sound Knowledge of Standard cells Circuit Design including combinatorial cells as well as complex Sequential Cells like Pulse Latches, Synchronizers, Multi-Bit Flop-Flops, Retention Flip-Flops, Rad-Hard Flops, Low Power/High Performance Flip-Flops, Other power management cells such as Isolation cells, Level Shifters, Power Switches etc.
Parasitic extraction & circuit optimization for Power/Performance/Area/Robustness
Should be able to co-relate various layout aspects to Circuit in order to design Optimal PPA Standard Cells
Hands-on of Industry standard simulation tools such as HSPICE is a must
Development of automation for library validation, quality checking, performance and reliability verification ex. Monte Carlo Functional Verification
Familiarity with ASIC design flow

For more & updated details, hit “Apply for job”