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Synopsys

Experience Required: 1 – 3 yrs Education: Btech/Mtech Electronics/Electrical engineering

Skills/Experience: – Knowledge of CMOS processes and issues in deep submicron process technologies. – CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. – Familiarity with ASIC design flow. – Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. – Ability to execute assigned circuit design tasks with best product quality and efficiency. – Good written and verbal communication skills in interactions with internal development teams.

Responsibilities: – DDR I/O Circuit and layout design including GPIO and Special IO’s. – Work with DDR PHY team, package engineers and system engineers to meet design specifications.

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