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Synopsys

We’re looking for a ASIC Digital Design Engineer, Staff to join the team.
Does this sound like a good role for you?
Technical lead role along with hands-on development responsibility.
Digital RTL development of one or more IPs in the “next-gen NRZ/PAM4 SERDES space”.
SERDES designs are made for protocols like Ethernet/PCIe/CPRI/JESD204C/etc.
Candidate will fully own the digital design for his IP.
The design involves complex calibration and adaptation algorithms between analog and digital.
Power optimization techniques need to be applied at architecture and implementation stages to make the design competitive.
Timing and area optimization planning is also required from architecture stage. Clock speed in digital is up to 3GHz.
Support of customer in IP integration, post silicon bringup and debug, answering technical questions.

For additional details and most recent updates, hit “Apply for job”