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Synopsys

We are looking for engineering graduates/PG students to work as interns in the field of VLSI.  Does this sound like a good role for you?

The role will be focused on VLSI design in the following areas related to connectivity protocols: DDR PHY.

The nature of the role will be:VLSI Design  of sub-blocks/exploration of latest features and standards.
Based on project assigned, the job would involve one or more of the following activities: Verilog/System Verilog
Exposure to UVM methodology, working with EDA tools like Design Compiler for Synthesis, SpyGlass for Lint, VCS for simulation.

For additional details and most recent updates, hit “Apply for job”