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Synopsys

12 to 15 years of experience in Emulation, FPGA prototyping or SoC Integration.
Bachelor/Master of Engineering/PhD in Electronics and Communication Engineering, Computer Science Engineering, Electrical or Electronics Engineering.
Must have hands on experience on Zebu or equivalent emulator.
Must have some experience in Architecting SoC’s, Processor as well as IP level Integration and SoC level Power Planning.
Must have experience in RTL coding (System Verilog, Verilog, VHDL etc).
Must have basic knowledge on SOC functional verification concepts.
Must have experience in C/C++ coding for test bench creation.
Scripting language knowledge like TCL, PERL and Python would be of added advantage
Protocol knowledge like AXI, USB, PCI, would be added advantage.

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