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Synopsys

As an analog design manager in the PLL design team, the candidate would supervise a team of engineers responsible for system-level and circuit-level PLL design. PLL designs will support Synopsys’ state of the art high-speed NRZ and PAM4 Serdes designs such as PCI-Express, Ethernet, JESD and CPRI, as well as other applications. The candidate will lead a team of designers based at Synopsys’ site in Hyderabad and collaborate with other design teams in India and North America

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