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Synopsys

Key Qualifications and Preferred Experience

-Required 4+ years of related experience.

-Experience in HDL language, Verilog and System Verilog.

-Knowledge of PCIe/CXL will be plus. –

-Knowledge of UVM and Functional verification will be a plus.

-Knowledge of programming concepts in C/C++, data structure will be a plus.

-Must be good in communication skills and as team player.

-Must be flexible, resourceful and responsible to complete assigned tasks within limited resources.

-Exercises judgment to determine appropriate action.

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