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Synopsys

We’re looking for an ASIC Mid-End Senior Implementation Engineer to join the team.

Responsibilities

To perform a key role in linking the front-end RTL design with the back-end physical implementation design and will drive alignment between the RTL design team and physical design team. It will provide technical oversight to the physical design team on the physical implementation of the controller and technical guidance to the RTL design team on the creation of designs to meet every more demanding timing-closure challenges.

The candidate(s) will be strong in RTL synthesis, constraint generation/validation and timing analysis. They will be capable of generating sub-systems consisting of controller, PHY and SRAM. They will be capable of defining floorplans and pushing the design through front-end placement flows. The successful candidate will be very familiar with physical design.

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