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Synopsys

Requirements
In depth familiarity with transistor level circuit design – sound CMOS design fundamentals
Exposure to SERDES subcircuits (ie. RX, TX, PLL, etc…)
Design for porting (ie. design so as to enable ease of moving circuits and layout across multiple foundry nodes)
Aware of ESD issues (ie. circuit techniques, layout)
Familiarity with custom digital design (ie. high speed logic paths)
Knowledge of design for reliability (ie. EM, IR, aging, etc…)
Knowledge of layout effects (ie. matching, reliability, proximity effects, etc…)
Familiar with CD and/or Cadence, HSPICE, HSIM
Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB etc…)
Some knowledge of system level budgeting (ie. jitter, amplitude, noise, etc…)
Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise)
Good communication and documentation skills
Experience with circuit modeling (ie. Verilog-A)

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