Job Description and Requirements

Seeking a highly motivated and innovative mixed signal AMS co-simulation verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products. The position offers an excellent opportunity to work with an expert team of digital, analog and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Responsibilities include:

modifying/using the existing UVM and VMM  SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment
analyzing/verifying the functionalities of SERDES;
Defining and tracking verification testplans;
Debugging simulation failures in both analog and digital domains;
Creating top level analog testbenches for SERDES;
Performing physic layout reliability analysis for SERDES;

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