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Synopsys

Hands-on experience in architecture evaluation, circuit level design and simulations of analog blocks Experience in design of one or more of the following: PLLs, ADC/DACs, SerDes modules such as driver, duty cycle corrector, receiver, equalizer, sampler, clock distribution etc. Experience with voltage references, LDOs and biasing circuits Understand multiple SerDes protocol requirements and create target electrical specification for link sub-systems Provide technical guidance to junior analog circuit designers and layout engineers Understand digital design concepts and work with digital design teams to develop and implement algorithms for calibration and adaptation of analog impairments Conduct and deliver design reviews within the team and with customers Should have very good knowledge of nanometer CMOS layout concepts, impact of layout parasitics and post layout simulations and review Should have most of the designed circuits proven on silicon with hands-on experience in silicon debug and characterization

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