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Synopsys

JD for Transactor requirement:

Development of RTL bus functional models and verification IP for various electronic interface standards Memory (DDRx, FLASH etc.) IP modeling in Verilog HDL/System Verilog Develop C/C++ API for communication with bus functional models based on Accelera SCE-MI standard and Synopsys proprietary technologies Simulation based verification of bus functional models and memory IP

Skill required:

Verilog HDL, System Verilog RTL modeling preferably with experience in FPGA based design/synthesis flows C/C++, Object Oriented Programming fundamentals Design verification methodologies using OVM/UVM, debugging using simulation tools Specific knowledge and experience of design and/or verification with one or more electronic interface standards such as PCIe, USB, MIPI, AMBA, HDMI/MHL etc. will be a plus Knowledge and experience with developing Verification IP based on Accelera SCEMI2.x standard will be a significant plus Experience with verification of designs on RTL/gate level logic emulators will be a significant plus Experience:- should have at least 4+ years of relevant experience in this domain.

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