Job Description and Requirements

Seeking a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities.
Responsibilities include floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM. The individual will contribute both on the implementation side as well as flow development for a variety of mixed signal IP & Subsystems products and test-chips at 16 nm and below.

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