Job Description and Requirements

Mixed-Signal IP organization seeking a highly motivated manager responsible for the physical implementation of complex and challenging interface IPs PHYs and Testchips for the most advanced technology nodes across foundries.

In such highly technical leadership position, you manage and grow a team responsible for the Physical implementation of high speed SerDes and DDR, driving all aspects of internal execution from RTL to GDS including timing and physical sign-off, using advanced technology nodes.
You negotiate and establish schedule and resource planning in close interaction and collaborative team work with internal teams.
The role also includes driving feasibility study and working with IP RTL teams to explore and converge on optimum trade-off for physical design closure on performance, power and area.

Preferred qualifications:

Proven track record of managing physical design Team for on-time delivery.
Physical Design experience with recent contribution to project tape-outs, as a technical driver and as project lead.
Hands-on experience and solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design: Synthesis, place and route, STA, formal verification, timing constraints, power/EM/IR analysis, Low power design. DFT.
In depth understanding on logical bottle necks impacting timing closure and methods to overcome these challenges.
Good communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.
Good software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.
Good understanding of industry standards in deep sub-micron designs
Easily work across cultures and locations
Autonomous, timely decision maker and able to cope with interrupts.

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