As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop testplan, testbench and testcases to verify mixed signal (digital and analog) designs.

Generates verification specifications.
Determines  test bench design and test cases.
Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
Generates documentation for test plans, verification environments, and usage.
Participate in evaluation and troubleshooting of digital and mixed signal designs.

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