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Synopsys

We are looking for a Senior Analog Design Engineer who will part of a SERDES high performance/high speed circuits development team, in particular, high demanded frequency clock generation with low noise, to address most advanced consumer 20Gbps protocols in the market.
Does this sound like a good role for you?

This role involves developing integer and fractional PLL circuits based on LC tank and Ring-Oscillator topologies, with low phase noise and low area and power consumption. You’d leverage your strong understanding of circuit simulation and circuit layout as well as knowledge of CMOS and RF circuitries, Phase-Detector, Charge-Pump. DLL and VCO architectures.

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