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Synopsys

The candidate will be working on:Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)
Generate verification test plan, verification environment documentation and test environment usage documentation
Define, develop, and verify complex UVM verification environments
Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage)
Identify design problems, possible corrective actions and/or inconsistencies on documented functionality

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