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Synopsys

Job Description and Requirements

RTL design.
•         FPGA design, implementation and timing closure using  Xilinx & Synopsys development tools.
•         Verify the design in simulation using SystemVerilog & UVM (Universal Verification Methodology).
•         Create user documentation.
•         Create test plans for USB IP.
•         Bringup and validate the design in the lab & generate test reports.
•         Perform HW validation tasks and debug IPs.
•         Read, understand and modify SW drivers and scripts.

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