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Synopsys

Synopsys Verification Group is looking for an R&D engineer to work on the performance and clock processing aspects of its ZeBu emulation platform.

Responsibilities:

Responsible for research and development of clock processing related optimizations.
Responsible for understanding performance aspects in ZeBu and identifying opportunities to improve it further.
Responsible for developing, testing, and tuning stable ASIC/FPGA algorithms targeting high quality of results (QoR) such as area, performance, congestion, compile time and power etc.
Designs, implements, tests, delivers, and maintains highly efficient algorithms and data structures.
Usually developing professional expertise and may apply company policies and procedures to resolve a variety of issues.
Exercises judgment to determine appropriate action. Implementations and solutions are reviewed for accuracy and overall adequacy.
Builds productive internal/external working relationships.
Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.

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