Job Description and Requirements

You will be a member of a high performing R&D team contributing to the development of market-leading interconnect parasitic extraction tool (StarRC).

StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.

Research, design, and development of brand-new extraction capabilities with special focus on   transistor level modeling.
Designing very efficient data structure and algorithms
Collaboration with other market leading product developers in layout design, simulations, timing/reliability verification areas
Communication with variety of customers on resolution of challenging problems in CPU design/validation/signoff/etc.

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