Synopsys

The primary focus of this Verification Applications Engineer is to support the sale and adoption of the Synopsys Verification solution – simulation and debug platform and System Verilog/UVM Testbench methodology. As a Verification AE, the candidate will be driving the effort to enable the verification methodology and solution for customers using Synopsys Verification tools (VCS). Engineer is expected to possess in-depth knowledge of RTL simulation and System Verilog/UVM testbench development with strong debugging skills. Candidate should have hands-on experience on UVM, Assertion and Randomized Constraints based verification methodologies. In this role AE will work directly with customers to assist with the deployment of the verification tools and methodologies, resolve technical issues and provide technical training.  The responsibilities includes product demonstrations, evaluations, and competitive benchmarking.

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