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Teradyne

Responsibilities
Seeking an FPGA/ASIC design engineer with 5+ years of product development experience to work with a local multi-disciplined team to design, code, and verify FPGA/ASICs in our cutting-edge products in a fast-paced, process-oriented environment.

•    Architecture, design, implementation, verification, and test of FPGAs for automated test equipment
•    Work with Hardware, Software and Systems engineering to define scalable, high-performance, high-quality, extensible, and maintainable FPGA devices and IP
•    Hands-on execution of product integration and verification testing and debug
Minimum qualifications:
•    Experience in developing and writing clear design specifications
•    Excellent coding skills in Verilog HDL.
•    Experience with physical design tools from FPGA vendors (Vivado or Quartus) or ASIC vendors.
•    Experience with timing constraints and timing closure on FPGA/ASIC designs.
•    Knowledge of memory interfaces (DDR)
•    Knowledge of communications protocols (Ethernet, PCIe, SPI, I2C, etc)
•    Ability to debug difficult problems using a variety of software and hardware tools (debugger, JTAG emulator, logic analyzer, and oscilloscope)
•    Highly motivated, team player, willing to pick up any piece of code, with a can-do attitude, and attracted to challenging opportunities

For additional details and most recent updates, hit “Apply for job”